`timescale 1ns/1ns
module mux8_1_test;

reg [7:0] inp;
reg [2:0] shift;
wire [7:0] outp;

mux_8 u1(inp,shift,outp);
initial
  begin
    inp=0;shift=0;
    #20 inp=7'd0;shift=3'd7;
    #20 inp=7'd1;shift=3'd7;
    #20 inp=7'd2;shift=3'd7;
    #20 inp=7'd3;shift=3'd7;
    #20 inp=7'd4;shift=3'd7;
    #20 inp=7'd5;shift=3'd7;
    #20 inp=7'd6;shift=3'd7;
    #20 inp=7'd63;shift=3'd7;
    
    #20 $stop;
 end
 initial $monitor($time, , ,"inp=%b shift=%b outp=%b",inp,shift,outp);
 endmodule
 